The present invention relates generally to microprocessor table write operations, and more specifically, to testing the optimization of microprocessor table functions.
Most microprocessors include arrays or tables consisting of multiple rows and columns, which are used to provide access to data at faster speeds than from off-chip storage. The tables are limited in size and encompass only a subset of the most recently used data, and the data may be organized according to least recently used (LRU) and most recently used (MRU) data, or information regarding the LRU and MRU data may be stored in the table or other memory locations. Typically, the cell data of the least recently used column of a row in a table is replaced by the most recent write operation. When there is a data write operation, cell data (row address, column number) might have to be replaced unless the current cell data is invalid. It has been proven to be most efficient to replace the data of the least recently used cell in this row (row address). To achieve this some hardware designs use a full LRU/MRU replacement strategy. Various systems with varying levels of complexity have been devised to implement LRU/MRU designs in microprocessors.
However, the verification of LRU/MRU designs increases in complexity as the complexity of the LRU/MRU design increases. In addition, a verification system that mirrors LRU/MRU hardware design too closely becomes less robust and loses generic qualities that would allow the verification system to be used with multiple LRU/MRU designs.